1. Field of the Invention
The present invention relates to a display device and a method of driving the same, and can be applied to an active matrix type display device having pixels each of which is composed of an organic Electro Luminescence (EL) device, for example, using a polysilicon Thin Film Transistor (TFT). The present invention is made such that a signal level of a write signal for an entire time period or a partial time period of a time period for which no influence is exerted on the drive for a light emitting device at all within a non-emission time period for which the light emitting device is stopped to emit a light is set at a signal level on a short time period side in other time periods except for the entire time period or the partial time period, thereby making it possible to effectively avoid a phenomenon that an image quality deteriorates due to a variation with age, and gradation cannot be set.
2. Description of the Related Art
In related art, the various techniques have been proposed for the display devices each of which is composed of the organic EL devices. These various techniques, for example, are described in U.S. Pat. No. 5,684,365, and Japanese Patent Laid-Open No. Hei 8-234683.
Here, FIG. 2 is a block diagram showing a so-called active matrix type display device, in the related art, using organic EL devices. In this active matrix type display device 1, a display portion 2 is formed by disposing pixels 3 in a matrix. In addition, in the display portion 2, scanning lines SCNs are horizontally distributed in units of lines for the pixels disposed in a matrix, and a signal line SIG is distributed every column so as to be perpendicular to the scanning lines SCNs.
Here, as shown in FIG. 3, each of the pixels 3 is composed of an organic EL device 8 as a current drive type self-light emitting device, and a drive circuit, of corresponding one of the pixels 3, for driving the organic EL device 8 (hereinafter referred to as “a pixel circuit”).
In the pixel 3, one terminal of a signal level holding capacitor C1 is held at a given potential, and the other terminal of the signal level holding capacitor C1 is connected to the signal line SIG through an transistor TR1 which is turned ON or OFF by a write signal WS. As a result, in the pixel 3, the transistor TR1 is turned ON in accordance with the rising of the write signal WS, and the potential at the other terminal of the signal level holding capacitor C1 is set at the signal level on the signal line SIG. In addition, the signal level on the signal line SIG is sampled and held at the other terminal of the signal level holding capacitor C1 with timing at which the transistor TR1 is switched from the ON state over to the OFF state.
In the pixel 3, the other terminal of the signal level holding capacitor C1 is connected to a gate of a P-channel TFT transistor TR2 having a source connected to a power source Vcc, and a drain of the transistor TR2 is connected to an anode of the organic EL device 8. Here, the pixel 3 is set such that the transistor TR2 usually operates in a saturation region. As a result, the transistor TR2 constitutes a constant current circuit based on a drain to source current Ids expressed by the following Expression (1):
                              I          ds                =                              1            2                    ⁢          μ          ⁢                                          ⁢                      W            L                    ⁢                                                    C                ox                            ⁡                              (                                                      V                    gs                                    -                                      V                    th                                                  )                                      2                                              (        1        )            
Where Vgs is a gate to source voltage of the transistor TR2, μ is a mobility, W is a channel width, L is a channel length, Cox is a capacity obtained based on a gate insulating film per unit area, and Vth is a threshold voltage of the transistor TR2. As a result, in each of the pixels 3, the organic EL device 8 is driven by the drive current Ids (drain to source current) corresponding to the signal level on the signal line SIG sampled and held in the signal level holding capacitor C1.
In the display device 1, predetermined sampling pulses are successively transferred by a write scanning circuit (WSCN) 4A of a vertical drive circuit 4 to generate write signals WS as timing signals to make instructions to successively write data to the pixels 3. In addition, predetermined sampling pulses are successively transferred by a horizontal selector (HSEL) 5A of a horizontal drive circuit 5 to successively generate timing signals. Also, each of the signal lines SIG is set at a signal level of an input signal S1 with each of the timing signals as a reference. As a result, the display device 1 sets a voltage across the terminals of the signal level holding capacitor C1 provided in the display portion 2 in accordance with the input signal S1, thereby displaying thereon an image corresponding to the input signal S1 in a dot-sequential or line-sequential manner.
Here, as shown in FIG. 4, current-voltage characteristics of the organic EL device 8 changes over time in a direction of causing a current to hardly flow due to the long term use. It is noted that in FIG. 4, a curve indicated by reference symbol L1 represents the initial current-voltage characteristics, and a curve indicated by reference symbol L2 represents the current-voltage characteristics due to the variation with age. However, when the organic EL device 8 is driven by the P-channel TFT transistor TR2 in the circuit configuration shown in FIG. 3, the transistor TR2 drives the organic EL device 8 in accordance with the gate to source voltage Vgs set in accordance with the signal level on the signal line SIG, thereby making it possible to prevent the luminance change in each of the pixels due to the variation with age of the current-voltage characteristics.
Now, when all the transistors constituting the pixel circuits, the horizontal drive circuit, and the vertical drive circuit are configured in the form of N-channel TFT transistors, these circuits can be collectively formed on an insulating substrate such as a glass substrate in the amorphous silicon process. As a result, the display device can be simply manufactured.
However, as shown in FIG. 5 in comparison with FIG. 3, when an N-channel TFT transistor is applied to the transistor TR2 to form each of pixels 13, and thus a display device 11 is composed of a display portion 12 having the pixels 13 formed therein, connecting a source of the transistor TR2 to the organic EL device 8 results in the problem that the gate to source voltage Vgs of the transistor TR2 changes due to the change in current-voltage characteristics shown in FIG. 4. As a result, in this case, the current flowing through the organic EL device 8 gradually decreases due to the long term use, which results in the problem that the emission luminance of the organic EL device 8 is reduced step by step. In addition, with the circuit configuration shown in FIG. 5, the emission luminance disperses every pixel due to the dispersion in the characteristics of the transistor TR2. It is noted that the dispersion in the emission luminance disturbs the uniformity in the displayed picture, and the disturbance is perceived in the form of color heterogeneity or roughness of the displayed picture.
For this reason, it is expected to configure each of pixels, for example, as shown in FIG. 6 as the technique for preventing the dispersion in the emission luminance due to the reduction in the emission luminance, and the dispersion in the characteristics which are caused by such a variation with age of the organic EL device.
Here, in a display device 21 shown in FIG. 6, a display portion 22 is formed by disposing pixels 23 in a matrix. In the pixel 23, one terminal of the signal level holding capacitor C1 is connected to the anode of the organic EL device 8. Also, the other terminal of the signal level holding capacitor C1 is connected to the signal line SIG through the transistor TR1 which is turned ON or OFF in accordance with the write signal WS. As a result, in the pixel 23, the voltage at the other terminal of the signal level holding capacitor C1 is set at the signal level on the signal line SIG in accordance with the write signal WS.
In the pixel 23, both terminals of the signal level holding capacitor C1 are connected to the source and the gate of the transistor TR2, respectively. Also, the drain of the transistor TR2 is connected to the scanning line SCN for supply of a power source voltage. As a result, in the pixel 23, the organic EL device 8 is driven by the transistor TR2 having a source follower circuit configuration in which the gate voltage is set at the signal level on the signal line SIG. It is noted that reference symbol Vcat designates a cathode potential of the organic EL device 8.
In the display circuit 21, a write scanning circuit (WSCN) 24A and a drive scanning circuit (DSCN) 24B of a vertical drive circuit 24 output a write signal WS and a drive signal DS for the power source to the scanning lines SCNs, respectively. In addition, a horizontal selector (HSEL) 25A of a horizontal drive circuit 25 outputs a drive signal Ssig to the signal line SIG. An operation of the pixel 23 is controlled in such a manner.
Here, FIGS. 7A to 7E are a time chart explaining the operation of the pixel 23. In the pixel 23, for an emission time period as a time period for which the organic EL device 8 emits a light, as shown in FIG. 8, the transistor TR1 is set in the OFF state by the write signal WS, and the power source voltage Vcc is supplied to the transistor TR2 by the drive signal DS (refer to FIGS. 7A and 7B). As a result, the gate voltage Vg and the source voltage Vs (refer to FIGS. 7D and 7E) of the transistor TR2 are held at the voltages at the both terminals of the signal level holding capacitor C1, respectively. Thus, the organic EL device 8 is driven by a drive signal Ids based on the gate voltage Vg and the source voltage Vs. It is noted that the drive signal Ids is expressed by Expression (1).
In the pixel 23, when the emission time period is completed, as shown in FIG. 9, the drain voltage of the transistor TR2 is dropped to a predetermined voltage Vss by the drive signal DS. Here, the predetermined voltage Vss is set at a voltage lower than a voltage obtained by adding the cathode voltage Vcat of the organic EL device 8 to a threshold voltage Vth of the organic EL device 8. As a result, the drive signal DS side of the transistor TR2 for drive functions as a source, and an anode voltage (Vs in FIG. 7E) of the organic EL device 8 rises, so that the organic EL device 8 stopped to emit the light.
At this time, in the pixel 23, as indicated by an arrow in FIG. 9, the accumulated charges are discharged from the organic EL device 8 side terminal of the signal level holding capacitor C1, whereby the anode voltage of the organic EL device 8 drops to be set at the voltage Vss.
Subsequently, in the pixel 23, as shown in FIG. 10, the signal level on the signal line SIG is dropped to a predetermined voltage Vofs by the drive signal Ssig, and the transistor TR1 is switched from the OFF state over to the ON state by the write signal WS (refer to FIGS. 7A and 7C). As a result, in the pixel 23, the gate voltage Vg of the transistor TR2 is set at the voltage Vofs of the signal line SIG, and the gate to source voltage Vgs of the transistor TR2 is set at (Vofs−Vss). Here, when a threshold voltage of the transistor TR2 is Vth, the voltage Vofs is set such that the gate to source voltage Vgs of the transistor TR2 is larger than the threshold voltage Vth of the transistor TR2.
Subsequently, for a time period designated by reference symbol Tth1 in FIGS. 7A to 7E, as shown in FIG. 11, the drain voltage of the transistor TR2 is dropped to the power source voltage Vcc by the drive signal DS in a state in which the transistor TR1 is held in the ON state. As a result, in the pixel 23, when the voltage across the terminals of the signal level holding capacitor C1 is larger than the threshold voltage of the transistor TR2, as indicated by an arrow in FIG. 11, a charge current flows from the power source Vcc into the organic EL device 8 side terminal of the signal level holding capacitor C1, so that a voltage Vs at the organic EL device 8 side terminal of the signal level holding capacitor C1 gradually rises. Here, an equivalent circuit of the organic EL device 8 is expressed in the form of a parallel circuit of a diode and a capacitor Cel. Here, in the state shown in FIG. 11, the current flows from the power source Vcc into the organic EL device 8 as well through the transistor TR2. However, a leakage current of the organic EL device 8 is considerably smaller than the current flowing through the transistor TR2 as long as the voltage across the terminals of the organic EL device 8 exceeds the threshold voltage of the organic EL device 8 due to the rise of the source voltage of the transistor TR2. Therefore, the current flowing into the organic EL device 8 is used to charge the signal level holding capacitor C1 and the capacitor Cel of the organic EL device 8 with electricity. As a result, in the pixel 23, the organic EL device 8 emits no light at all, and only the source voltage of the transistor TR2 merely rises.
Subsequently, in the pixel 23, the transistor TR1 is switched from the ON state over to the OFF state by the write signal WS, and the signal level of the signal on the signal line SIG is set at a signal level Vsig representing the gradation of the corresponding pixel belonging to the signal line adjacent to the signal line SIG but one. As a result, in the pixel 23, the charge current continuously flows from the power source Vcc into the organic EL device 8 side terminal of the signal level holding capacitor C1 through the transistor TR2, so that the source voltage Vs of the transistor TR2 continues to rise. In addition, in this case, the gate voltage Vg of the transistor TR2 rises so as to follow the rise in the source voltage Vs of the transistor TR2. It is noted that the signal level Vsig on the signal line SIG for this time period is used to set the gradation for the corresponding pixel belonging to the signal line adjacent to the signal line SIG but one.
In the pixel 23, after a lapse of a given time, the signal level on the signal line SIG is switched over to the voltage Vofs again. As a result, for a time period designated by reference symbol Tth2 in FIGS. 7A to 7E, when the voltage across the terminals of the signal level holding capacitor C1 is larger than the threshold voltage of the transistor TR2 in the state in which the signal line SIG side potential of the signal level holding capacitor C1 is held at the voltage Vofs, the charge current flows from the power source Vcc into the organic EL device 8 side terminal of the signal level holding capacitor C1 through the transistor TR2, so that the source voltage Vs of the transistor TR2 gradually rises. As a result, as shown in FIG. 12, the source voltage Vs of the transistor TR2 rises step by step so that the gate to source voltage Vgs of the transistor TR2 approaches the threshold voltage Vth of the transistor TR2. Also, when the gate to source voltage Vgs of the transistor TR2 comes to be equal to the threshold voltage Vth of the transistor TR2, the inflow of the charge current into the organic EL device 8 side terminal of the signal level holding capacitor C1 through the transistor TR2 is stopped.
In the pixel 23, the processing for the inflow of the charge current into the organic EL device 8 side terminal of the signal level holding capacitor C1 through the transistor TR2 is repeatedly executed given times enough for the gate to source voltage Vgs of the transistor TR2 to come to be equal to the threshold voltage Vth of the transistor TR2 (three times designated by reference numerals Tth1, Tth2 and Tth3 in the example shown in FIGS. 7A to 7E). As a result, as shown in FIG. 13, the threshold voltage Vth of the transistor TR2 is set in the signal level holding capacitor C1. It is noted that in the pixel 23, the voltages Vofs and Vcat are set so that a relationship of Vel=Vofs−Vth<Vcat+Vthel where Vthel is a threshold voltage of the organic EL device 8 is obtained in a state in which the threshold voltage Vth of the transistor TR2 is set in the signal level holding capacitor C1. As a result, the setting is performed so that the organic EL device 8 emits no light at all.
After that, in the pixel 23, the potential at the signal line SIG side terminal of the signal level holding capacitor C1 is set at the voltage Vsig representing the emission luminance of the organic EL device 8, whereby the voltage representing the gradation is set in the signal level holding capacitor C1 so as to cancel the threshold voltage Vth of the transistor TR2. As a result, there is prevented the dispersion in the emission luminance due to the dispersion in the threshold voltage Vth of the transistor TR2.
That is to say, as shown in FIG. 14, in the pixel 23, after a lapse of the time period Tth3, the signal level on the signal line SIG is set at the signal level Vsig representing the emission luminance of the pixel 23 concerned. Subsequently, as shown by a time period Tμ, the transistor TR1 is set in the ON state by the write signal WS. As a result, in the pixel 23, the signal level at the signal line SIG side terminal of the signal level holding capacitor C1 is set at the signal level Vsig on the signal line SIG. Also, the current corresponding to the gate to source voltage Vgs based on the voltage across the terminals of the signal level holding capacitor C1 flows from the power source Vcc into the signal level holding capacitor C1 side terminal of the organic EL device 8 through the transistor TR2. As a result, the source voltage Vs of the transistor TR2 gradually rises.
Here, the current flowing from the power source Vcc into the signal level holding capacitor C1 side terminal of the organic EL device 8 through the transistor TR2 changes in accordance with a mobility of the transistor TR2. Thus, as shown in FIG. 15, the rise speed of the source voltage Vs increases with an increase in mobility of the transistor TR2. In addition, the current flowing through the transistor TR2 for driving the organic EL device 8 while the organic EL device 8 emits the light also increases depending on the mobility of the transistor TR2. Thus, there is a disadvantage that the dispersion in the threshold voltage Vth and the dispersion in the mobility μ are large because this sort of transistor TR2 is a polysilicon TFT or the like.
Thus, in the pixel 23, for the time period designated by reference symbol Tμ, the transistor TR2 is turned ON to cause the charge current to flow into the organic EL device 8 side terminal of the signal level holding capacitor C1 in the state in which the signal line SIG side voltage of the signal level holding capacitor C1 is held at the signal level Vsig on the signal line SIG. As a result, the voltage across the terminals of the signal level holding capacitor C1 is reduced by the degree corresponding to the mobility of the transistor TR2, thereby preventing the dispersion in the emission luminance due to the dispersion in the mobility of the transistor TR2.
In the pixel 23, after a lapse of the given time period Tμ, the transistor TR1 is turned OFF by the write signal WS, and the signal level Vsig of the signal on the signal line SIG is held in the signal level holding capacitor C1, thereby starting the emission time period. It is noted that from these facts, the drive signal Ssig for the signal line SIG is repeated in a state in which the fixed potential Vofs is held between the signal levels Vsig which represent the gradations in order of the pixels 23 connected to one signal line.
Now, in the polysilicon TFT or the like, as shown in FIG. 16, when the gate voltage Vg is held as a positive voltage with respect to the source voltage Vs, the threshold voltage Vth increases with time. Contrary to this, as shown in FIG. 17, when the gate voltage Vg is held as a negative voltage with respect to the source voltage Vs, the threshold voltage Vth decreases with time. Note that, in FIGS. 16 and 17, curves designated by reference symbols L3 and L4 represent an initial state and a state after the variation with age, respectively.
On the other hand, in the pixel 23, as shown in FIGS. 7A to 7E, the transistor TR1 is set in the ON state by the write signal WS only for a limited time period within a non-emission time period. As a result, the threshold voltage Vth of the transistor TR1 decreases step by step due to the long term use. It is noted that the non-emission time period corresponds to several time periods for the horizontal scanning of the time period of one frame. When the threshold voltage Vth of the transistor TR1 decreases step by step in such a manner, as shown in FIG. 18, the time period for which the transistor TR1 is held in the ON state increases to a time period of TON. As a result, in the pixel 23, the time periods Tth1 to Tth3 for which the threshold voltage of the transistor TR2 is corrected, and the time period Tμ for which the mobility of the transistor TR2 is corrected are lengthened, which results in the problem that the mobility of the transistor TR2 is over-corrected. This leads to that the color heterogeneity, of the image quality, such as the shading is generated due to the variation with age. In addition, when the threshold voltage Vth of the transistor TR1 is over-reduced, in the end, the transistor TR1 cannot be set in the ON state, which results in the problem that the gradation of the pixel 23 cannot be set.
As a result, the display device having the configuration in the related art involves such a problem that the image quality deteriorates due to the variation with age, and further the gradation cannot be set.